1. Field of the Invention
The present invention relates to a circuit for providing a power to a circuit block, e.g., a clock circuit and logic circuit.
2. Description of Related Art
In a semiconductor integrated circuit, accompanied by a high velocity of a clock, an improvement of a clock skew is required. Causes of the clock skew include, an error caused when the semiconductor integrated circuit is designed, a uniformity in a manufacturing process of the semiconductor integrated circuit, a clock jitter, or the like. Especially, the clock jitter due to a noise caused by a power supply may be a large part of the cause of the clock skew. By preventing a transmission of the noise caused by the power supply for a logic circuit to a clock circuit, the clock jitter may be reduced. However, when it is attempted to separate the power supply of the clock circuit from the power supply of the logic circuit, manufacturing processes and a circuit space may be increased because of the separation of the power supplies.
A clock distribution circuit of the semiconductor integrated circuit has often been designed by using a design tool popularly known as CTS (Clock Tree Synthesis). In this case, since the clock circuit is disposed in a same area for a standard cell (SC) of the logic circuit, it is impossible to separate the power supply of the clock circuit and the power supply of the logic circuit.
Further, to separate the power supply of the clock circuit from the power supply of the logic circuit, the clock circuit is designed as a specific circuit block (e.g., macro block) rather than the standard cell of the logic circuit, the specific block is located so as not to intervene in the standard cell, and then the power supply and a ground for the clock circuit are separated from those of the standard cell of the logic circuit. However, the specific block of the clock circuit is not able to be located in an area for the standard cell of the logic circuit.
Further, since the ground of the clock circuit and the ground of the logic circuit are separated and a resistor is added for connecting the ground and the clock circuit, a potential difference is generated between the ground for the clock circuit and the ground for the logic circuit by the noise of the power supply. By the potential difference, a discrepancy is caused between a threshold voltage of a transistor for the clock circuit and a threshold voltage of a transistor for the logic circuit, thereby to cause a skew.
In a semiconductor integrated circuit, when the standard cells of the clock circuit and the logic circuit are disposed without distinction, the clock skew is generated by the noise caused by the power supply of the logic circuit.
As clock frequency becomes higher, the clock skew becomes larger. Therefore, the technique for separating the power supply of the clock circuit from the power supply of the logic circuit is used for reducing the clock skew.
FIG. 6 shows a related art for separating the power supply of the clock circuit from the power supply of the logic circuit. In the related art, the power supply of the logic circuit is eliminated partially, and the macro block of the clock circuit is placed at the partially eliminated region.
In FIG. 6, reference numeral 41 shows the eliminated region, and reference numeral 42 shows the macro block of the clock circuit disposed at the eliminated region 41.
In the related art, since the macro block of the clock circuit needs to be designed, a design process of the semiconductor integrated circuit increases. Also, since it is required to eliminate the region, the design process of the semiconductor integrated circuit increases. Further, since a process for connecting the macro block and the power supply is required, the design process of the semiconductor integrated circuit increases.
The eliminated region needs to be larger than a size of the macro block of the clock circuit. As a result, in the eliminated region, there may be a region that a circuit element cannot be placed. Therefore, as the clock circuit size increases, the eliminated region of the power supply of the logic circuit increases, and then it becomes difficult to provide the power to the logic circuit.
Patent Document 1 discloses the technique for separating the power supply line. The drain side power supply lines between a circuit block A and a circuit block B which are separated in the power supply are connected by a plurality of resistors R. The source side power supply lines between the circuit block A and the circuit block B are connected by a plurality of resistors R. Signal propagation elements B1 and B2 are disposed by corresponding to the connecting points of each resistor R. A signal transmitted between the circuit block A and the circuit block B is transmitted through the signal propagation elements B1 and B2.
In the Patent Document 1, a malfunction caused by the power supply noise may be reduced independently of the frequency of the signal propagated between the circuit block A and the circuit block B. The signal propagated between the circuit block A and the circuit block B may be stable without installing a specific circuit, such as a low pass filter and a high frequency clock generating circuit, into an LSI.
In the Patent Document 1, the power supply of the clock circuit is connected to the power supply of the logic circuit. Therefore, in the Patent Document 1, the power supply of the clock circuit is not separated from the power supply of the logic circuit.
In Patent Document 2, a capacitor for a power supply and a clock driver are installed at a region under a wiring for supplying power. Therefore, the power is stably supplied from the power supply.
In Patent Document 3, a first wiring for supplying power to a logic circuit and a second wiring for supplying power to a clock circuit are installed in an LSI. A power supply for supplying the power to the first and the second wirings are installed on a first layer, the first layer being different from the second layer on which the first or second wiring is installed. Therefore, a power supply noise caused by the logic circuit is reduced, and thus a clock jitter is reduced.
In Patent Document 4, a design process of a clock circuit is disclosed. In the design process, re-design of a layout of the clock circuit is not required each time when a layout of a circuit other than the clock circuit is re-designed. Therefore, since re-design for laying-out the clock circuit is not required, factors affecting performance of the LSI, such as a clock jitter, are easily predictable.
In Patent Document 5, a power supply for a clock buffer cell which provides a clock signal and a power supply for a sub-clock buffer cell which provides a clock signal, are separated with each other. Each power supply is connected to another power source. Therefore, an influence caused by a power supply noise is dispersed, and thus a delay of the clock buffer cell and the sub-clock buffer cell is decreased.
[Patent Document 1] Japanese Patent Laid-Open No. 2006-054235
[Patent Document 2] Japanese Patent Laid-Open No. 2006-245384
[Patent Document 3] Japanese Patent Laid-Open No. 2006-318967
[Patent Document 4] Japanese Patent Laid-Open No. 9-213887
[Patent Document 5] Japanese Patent Laid-Open No. 11-204649